On 06/12/2022 16:23, Richard Henderson wrote:
On 12/6/22 10:02, Peter Maydell wrote:
On Tue, 6 Dec 2022 at 15:56, Philippe Mathieu-Daudé wrote:
On 6/12/22 13:30, Dr. David Alan Gilbert wrote:
I don't know that bit of qemu well enough to know whether the cpu part
of qemu should be splitting
On Tue, Dec 6, 2022 at 5:32 AM Dr. David Alan Gilbert
wrote:
> From intel arch manual 19.3:
> '..16-bit ports should be aligned to even addresses (0, 2, 4, ...) so
> that all 16 bits can be transferred in a
> single bus cycle. Likewise, 32-bit ports should be aligned to addresses
> that are mu
On 12/6/22 10:02, Peter Maydell wrote:
On Tue, 6 Dec 2022 at 15:56, Philippe Mathieu-Daudé wrote:
On 6/12/22 13:30, Dr. David Alan Gilbert wrote:
I don't know that bit of qemu well enough to know whether the cpu part
of qemu should be splitting the unaligned accesses or not.
All I/O accesses
On 6/12/22 15:38, Gerd Hoffmann wrote:
Hi,
So on x86 we can have 16-bit I/O accesses unaligned to 8-bit boundary?
Yes.
So I _think_ today we should be good with removing the x86 line:
-# ifdef TARGET_I386
-{ 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
-#
On Tue, 6 Dec 2022 at 15:56, Philippe Mathieu-Daudé wrote:
>
> On 6/12/22 13:30, Dr. David Alan Gilbert wrote:
> > I don't know that bit of qemu well enough to know whether the cpu part
> > of qemu should be splitting the unaligned accesses or not.
> All I/O accesses are gated thru access_with_adj
On 6/12/22 13:30, Dr. David Alan Gilbert wrote:
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
Hi,
I'm trying to understand the x86 architecture-specific code in
hw/display/vga.c:
const MemoryRegionPortio vbe_portio_list[] = {
{ 0, 1, 2, .read = vbe_ioport_read_index,
Hi,
> So on x86 we can have 16-bit I/O accesses unaligned to 8-bit boundary?
Yes.
> So I _think_ today we should be good with removing the x86 line:
>
> -# ifdef TARGET_I386
> -{ 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data
> },
> -# endif
Nope. Breaks vgabios.
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
> Hi,
>
> I'm trying to understand the x86 architecture-specific code in
> hw/display/vga.c:
>
> const MemoryRegionPortio vbe_portio_list[] = {
> { 0, 1, 2, .read = vbe_ioport_read_index,
>.write = vbe_ioport_writ
Hi,
I'm trying to understand the x86 architecture-specific code in
hw/display/vga.c:
const MemoryRegionPortio vbe_portio_list[] = {
{ 0, 1, 2, .read = vbe_ioport_read_index,
.write = vbe_ioport_write_index },
# ifdef TARGET_I386
{ 1, 1, 2, .read = vbe
