> -Original Message-
> From: Richard Henderson
> Sent: Thursday, January 26, 2023 3:48 PM
> To: Sid Manning ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; Mark Burton ; Alex
> Bennée
> Subject: Re: ARM: ptw.c:S1_ptw_translate
>
> WARNING: This email
Please try the following. It's essentially the same bug I had for mte.
I've just realized that the testing I did under Linux with virtualization=on
was insufficient -- this path won't be exercised without KVM under TCG.
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 57f3615a66..2b125fff
On 1/25/23 13:27, Sid Manning wrote:
On 7.2 VA to PA mappings are not consistent:
Thread 10 "vp" hit Breakpoint 1, tlb_add_large_page (env=0xeb7ac0,
mmu_idx=0x2, vaddr=0xff809977f000, size=0x1000) at
../../../../../../src/qemu/accel/tcg/cputlb.c:1090
tlb_set_page_full: vaddr=ff809977
Cc: phi...@linaro.org; Mark Burton
> Subject: RE: ARM: ptw.c:S1_ptw_translate
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
>
> > -Original Message-
> > From: Richard Henders
> -Original Message-
> From: Richard Henderson
> Sent: Wednesday, January 4, 2023 11:42 PM
> To: Sid Manning ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; Mark Burton
> Subject: Re: ARM: ptw.c:S1_ptw_translate
>
> WARNING: This email originated from outsid
On 1/4/23 08:55, Sid Manning wrote:
ptw.c:S1_ptw_translate
After migrating to v7.2.0, an issue was found where we were not getting the correct
virtual address from a load insn. Reading the address used in the load insn from the
debugger resulted in the execution of the insn getting the correc
Cc'ing Richard & qemu-arm list.
On 4/1/23 17:55, Sid Manning wrote:
ptw.c:S1_ptw_translate
After migrating to v7.2.0, an issue was found where we were not getting
the correct virtual address from a load insn. Reading the address used
in the load insn from the debugger resulted in the executi
