On Wed, 27 Apr 2022 at 07:10, Cédric Le Goater wrote:
>
> Hello,
>
> On 4/27/22 08:21, Joel Stanley wrote:
> > On Tue, 26 Apr 2022 at 12:51, Lucas Mateus Castro(alqotel)
> > wrote:
> >>
> >> From: "Lucas Mateus Castro (alqotel)"
> >>
> >> This patch series is an RFC of the Matrix-Multiply Assist
Something I forgot to mention in the cover letter, the XVFGER
instructions accumulate the exception status and at the end set the
FPSCR and take a Program interrupt on a trap-enabled exception, but as
the exception functions are currently set up in target/ppc/fpu_helper.c
a call to set a FPSCR
Hello,
On 4/27/22 08:21, Joel Stanley wrote:
On Tue, 26 Apr 2022 at 12:51, Lucas Mateus Castro(alqotel)
wrote:
From: "Lucas Mateus Castro (alqotel)"
This patch series is an RFC of the Matrix-Multiply Assist (MMA)
instructions implementation from the PowerISA 3.1
These and the VDIV/VMOD imp
On Tue, 26 Apr 2022 at 12:51, Lucas Mateus Castro(alqotel)
wrote:
>
> From: "Lucas Mateus Castro (alqotel)"
>
> This patch series is an RFC of the Matrix-Multiply Assist (MMA)
> instructions implementation from the PowerISA 3.1
>
> These and the VDIV/VMOD implementation are the last new PowerISA
