"Thiemo Seufer" <[EMAIL PROTECTED]> wrote:
The Qemu has a bug there. The "See MIPS Run" p.51 states:
A patch which doesn't negate the HFLAGS_UM check fixes this and was
posted here a while ago.
Thx, found.
http://lists.gnu.org/archive/html/qemu-devel/2006-03/msg00148.html
Is it possible to p
Alexander Voropay wrote:
[snip]
> Unfortunately, this code clears CU0 bits in the CP0(SR).
> It makes CP0 unusable for program and causes an exception 11 :
> Coprocessor Unusable on the next CP0 access.
>
> The Qemu has a bug there. The "See MIPS Run" p.51 states:
>
> CU0 - Coprocessor 0 usable;
"Alexander Voropay" <[EMAIL PROTECTED]> wrote:
Another issue:
IN:
0xbfc00424: mtc0 zero,$13
0x0001: raise_exception 0x11
The problem is a code *before* this :
==
mfc0v0,C0_SR
and v0,SR_SR# preserve Soft Reset
or v0,SR_BEV
