Re: [Qemu-devel] [RFC] target-arm: provide skeleton for a64 insn decoding

2013-11-12 Thread Alex Bennée
claudio.font...@linaro.org writes: > provide a skeleton for a64 instruction decoding in translate-a64.c, > by dividing instructions into the classes defined by the > ARM Architecture Reference Manual(DDI0487A_a) C3 > > Signed-off-by: Claudio Fontana > --- > The following patch has been started d

Re: [Qemu-devel] [RFC] target-arm: provide skeleton for a64 insn decoding

2013-11-11 Thread Richard Henderson
On 11/12/2013 01:13 AM, Claudio Fontana wrote: > +/* C3.2 Branches, exception generating and system instructions */ > +static void disas_b_exc_sys(DisasContext *s, uint32_t insn) > +{ > +switch (extract32(insn, 25, 7)) { > +case 0x0a: case 0x4a: /* Unconditional branch (immediate) */ > +