Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-04-11 Thread Eric Blake
On 04/10/2018 03:04 AM, Antony Pavlov wrote: +++ b/include/hw/riscv/sifive_uart.h + +typedef struct SiFiveUARTState { +/*< private >*/ +SysBusDevice parent_obj; >>> >>> >>> You use SysBusDevive in this header file but there is no 'include >>> "hw/sysbus.h"' in th

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-04-11 Thread Michael Clark
On Tue, Apr 10, 2018 at 8:04 PM, Antony Pavlov wrote: > On Tue, 10 Apr 2018 08:17:32 +0200 > Thomas Huth wrote: > > > On 10.04.2018 05:21, Antony Pavlov wrote: > > > On Sat, 3 Mar 2018 02:51:47 +1300 > > > Michael Clark wrote: > > > > > >> QEMU model of the UART on the SiFive E300 and U500 ser

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-04-10 Thread Antony Pavlov
On Tue, 10 Apr 2018 08:17:32 +0200 Thomas Huth wrote: > On 10.04.2018 05:21, Antony Pavlov wrote: > > On Sat, 3 Mar 2018 02:51:47 +1300 > > Michael Clark wrote: > > > >> QEMU model of the UART on the SiFive E300 and U500 series SOCs. > >> BBL supports the SiFive UART for early console access v

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-04-09 Thread Thomas Huth
On 10.04.2018 05:21, Antony Pavlov wrote: > On Sat, 3 Mar 2018 02:51:47 +1300 > Michael Clark wrote: > >> QEMU model of the UART on the SiFive E300 and U500 series SOCs. >> BBL supports the SiFive UART for early console access via the SBI >> (Supervisor Binary Interface) and the linux kernel SBI

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-04-09 Thread Antony Pavlov
On Sat, 3 Mar 2018 02:51:47 +1300 Michael Clark wrote: > QEMU model of the UART on the SiFive E300 and U500 series SOCs. > BBL supports the SiFive UART for early console access via the SBI > (Supervisor Binary Interface) and the linux kernel SBI console. > > The SiFive UART implements the pre q

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-03-16 Thread Bastian Koppelmann
On 03/16/2018 07:36 PM, Michael Clark wrote: > On Fri, Mar 16, 2018 at 11:30 AM, Michael Clark wrote: > >> >> >> On Sun, Mar 11, 2018 at 4:43 AM, Bastian Koppelmann < >> kbast...@mail.uni-paderborn.de> wrote: >> >>> Hi Mark, >>> >>> On 03/10/2018 10:40 AM, Mark Cave-Ayland wrote: On 10/03/18

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-03-16 Thread Michael Clark
On Fri, Mar 16, 2018 at 11:30 AM, Michael Clark wrote: > > > On Sun, Mar 11, 2018 at 4:43 AM, Bastian Koppelmann < > kbast...@mail.uni-paderborn.de> wrote: > >> Hi Mark, >> >> On 03/10/2018 10:40 AM, Mark Cave-Ayland wrote: >> > On 10/03/18 03:02, Michael Clark wrote: >> > >> >> On Sat, Mar 10, 2

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-03-16 Thread Michael Clark
On Sun, Mar 11, 2018 at 4:43 AM, Bastian Koppelmann < kbast...@mail.uni-paderborn.de> wrote: > Hi Mark, > > On 03/10/2018 10:40 AM, Mark Cave-Ayland wrote: > > On 10/03/18 03:02, Michael Clark wrote: > > > >> On Sat, Mar 10, 2018 at 1:39 AM, Philippe Mathieu-Daudé < > f4...@amsat.org> > >> wrote:

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-03-11 Thread Bastian Koppelmann
Hi Mark, On 03/10/2018 10:40 AM, Mark Cave-Ayland wrote: > On 10/03/18 03:02, Michael Clark wrote: > >> On Sat, Mar 10, 2018 at 1:39 AM, Philippe Mathieu-Daudé >> wrote: >> [...] > Another general note: for each of the main QEMU platforms supported > there is a home page on the official wiki, so

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-03-10 Thread Mark Cave-Ayland
On 10/03/18 03:02, Michael Clark wrote: On Sat, Mar 10, 2018 at 1:39 AM, Philippe Mathieu-Daudé wrote: On 03/02/2018 02:51 PM, Michael Clark wrote: QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Bi

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-03-09 Thread Michael Clark
On Sat, Mar 10, 2018 at 1:39 AM, Philippe Mathieu-Daudé wrote: > On 03/02/2018 02:51 PM, Michael Clark wrote: > > QEMU model of the UART on the SiFive E300 and U500 series SOCs. > > BBL supports the SiFive UART for early console access via the SBI > > (Supervisor Binary Interface) and the linux k

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

2018-03-09 Thread Philippe Mathieu-Daudé
On 03/02/2018 02:51 PM, Michael Clark wrote: > QEMU model of the UART on the SiFive E300 and U500 series SOCs. > BBL supports the SiFive UART for early console access via the SBI > (Supervisor Binary Interface) and the linux kernel SBI console. > > The SiFive UART implements the pre qom legacy int