On Fri, 2014-06-06 at 01:36 +0200, Alexander Graf wrote:
>
> It would be nicer if the guest had full control over the virtual
> address range of a PCI device.
It does ... within a HW window which can be different between P7 and
P8.
On P7 all PEs on a PHB share a single DMA address space that ge
On 06/06/2014 09:36 AM, Alexander Graf wrote:
>
> On 06.06.14 01:17, Alexey Kardashevskiy wrote:
>> On 06/06/2014 02:51 AM, Alexander Graf wrote:
>>> On 05.06.14 16:33, Alexey Kardashevskiy wrote:
On 06/05/2014 11:36 PM, Alexander Graf wrote:
> On 05.06.14 15:33, Alexey Kardashevskiy wrot
On 06.06.14 01:17, Alexey Kardashevskiy wrote:
On 06/06/2014 02:51 AM, Alexander Graf wrote:
On 05.06.14 16:33, Alexey Kardashevskiy wrote:
On 06/05/2014 11:36 PM, Alexander Graf wrote:
On 05.06.14 15:33, Alexey Kardashevskiy wrote:
On 06/05/2014 11:15 PM, Alexander Graf wrote:
On 05.06.14
On 06/06/2014 02:51 AM, Alexander Graf wrote:
>
> On 05.06.14 16:33, Alexey Kardashevskiy wrote:
>> On 06/05/2014 11:36 PM, Alexander Graf wrote:
>>> On 05.06.14 15:33, Alexey Kardashevskiy wrote:
On 06/05/2014 11:15 PM, Alexander Graf wrote:
> On 05.06.14 15:10, Alexey Kardashevskiy wrot
On 05.06.14 16:33, Alexey Kardashevskiy wrote:
On 06/05/2014 11:36 PM, Alexander Graf wrote:
On 05.06.14 15:33, Alexey Kardashevskiy wrote:
On 06/05/2014 11:15 PM, Alexander Graf wrote:
On 05.06.14 15:10, Alexey Kardashevskiy wrote:
On 06/05/2014 11:06 PM, Alexander Graf wrote:
On 05.06.14
On 06/05/2014 11:36 PM, Alexander Graf wrote:
>
> On 05.06.14 15:33, Alexey Kardashevskiy wrote:
>> On 06/05/2014 11:15 PM, Alexander Graf wrote:
>>> On 05.06.14 15:10, Alexey Kardashevskiy wrote:
On 06/05/2014 11:06 PM, Alexander Graf wrote:
> On 05.06.14 08:43, Alexey Kardashevskiy wrot
On 05.06.14 15:33, Alexey Kardashevskiy wrote:
On 06/05/2014 11:15 PM, Alexander Graf wrote:
On 05.06.14 15:10, Alexey Kardashevskiy wrote:
On 06/05/2014 11:06 PM, Alexander Graf wrote:
On 05.06.14 08:43, Alexey Kardashevskiy wrote:
On 06/05/2014 03:49 PM, Alexey Kardashevskiy wrote:
POWER
On 06/05/2014 11:15 PM, Alexander Graf wrote:
>
> On 05.06.14 15:10, Alexey Kardashevskiy wrote:
>> On 06/05/2014 11:06 PM, Alexander Graf wrote:
>>> On 05.06.14 08:43, Alexey Kardashevskiy wrote:
On 06/05/2014 03:49 PM, Alexey Kardashevskiy wrote:
> POWER KVM supports an KVM_CAP_SPAPR_TC
On 05.06.14 15:10, Alexey Kardashevskiy wrote:
On 06/05/2014 11:06 PM, Alexander Graf wrote:
On 05.06.14 08:43, Alexey Kardashevskiy wrote:
On 06/05/2014 03:49 PM, Alexey Kardashevskiy wrote:
POWER KVM supports an KVM_CAP_SPAPR_TCE capability which allows allocating
TCE tables in the host ker
On 06/05/2014 11:06 PM, Alexander Graf wrote:
>
> On 05.06.14 08:43, Alexey Kardashevskiy wrote:
>> On 06/05/2014 03:49 PM, Alexey Kardashevskiy wrote:
>>> POWER KVM supports an KVM_CAP_SPAPR_TCE capability which allows allocating
>>> TCE tables in the host kernel memory and handle H_PUT_TCE reque
On 05.06.14 08:43, Alexey Kardashevskiy wrote:
On 06/05/2014 03:49 PM, Alexey Kardashevskiy wrote:
POWER KVM supports an KVM_CAP_SPAPR_TCE capability which allows allocating
TCE tables in the host kernel memory and handle H_PUT_TCE requests
targeted to specific LIOBN (logical bus number) right
On 06/05/2014 03:49 PM, Alexey Kardashevskiy wrote:
> POWER KVM supports an KVM_CAP_SPAPR_TCE capability which allows allocating
> TCE tables in the host kernel memory and handle H_PUT_TCE requests
> targeted to specific LIOBN (logical bus number) right in the host without
> switching to QEMU. At t
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