On 06/13/16 12:07, Paolo Bonzini wrote:
>
>
> On 13/06/2016 12:01, Haozhong Zhang wrote:
> > > I would prefer to avoid having to change the firmware (SeaBIOS and OVMF)
> > > every time a new bit is added. Using fw_cfg makes it possible to
> > > develop the feature in the firmware once and for al
On 13/06/2016 12:01, Haozhong Zhang wrote:
> > I would prefer to avoid having to change the firmware (SeaBIOS and OVMF)
> > every time a new bit is added. Using fw_cfg makes it possible to
> > develop the feature in the firmware once and for all.
>
> Thanks for the explanation! Is it proper to
On 06/13/16 10:33, Paolo Bonzini wrote:
>
>
> On 13/06/2016 09:55, Haozhong Zhang wrote:
> > Currently, only VMX bits (bit 1 & 2), LMCE bit (bit 20) as well as
> > lock bit (bit 0) in MSR_IA32_FEATURE_CONTROL are used for guest. The
> > availability of features indicated by those bits (except the
On 13/06/2016 09:55, Haozhong Zhang wrote:
> Currently, only VMX bits (bit 1 & 2), LMCE bit (bit 20) as well as
> lock bit (bit 0) in MSR_IA32_FEATURE_CONTROL are used for guest. The
> availability of features indicated by those bits (except the lock bit)
> can be discovered from cpuid and other
On 06/08/16 13:32, Paolo Bonzini wrote:
>
>
> On 03/06/2016 17:57, Radim Krčmář wrote:
> >> > +cenv->msr_ia32_feature_control |=
> >> > +MSR_IA32_FEATURE_CONTROL_LMCE |
> >> > +MSR_IA32_FEATURE_CONTROL_LOCKED;
> > Locking right from the star
On 06/08/16 13:34, Paolo Bonzini wrote:
>
>
> On 05/06/2016 17:41, Haozhong Zhang wrote:
> > On 06/04/16 12:34, Boris Petkov wrote:
> >> Haozhong Zhang wrote:
> >>
> >>> This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
> >>> will be injected to only one VCPU rather than bro
On 03/06/2016 17:57, Radim Krčmář wrote:
>> > +cenv->msr_ia32_feature_control |=
>> > +MSR_IA32_FEATURE_CONTROL_LMCE |
>> > +MSR_IA32_FEATURE_CONTROL_LOCKED;
> Locking right from the start breaks nested KVM, because nested relies on
> settin
On 05/06/2016 17:41, Haozhong Zhang wrote:
> On 06/04/16 12:34, Boris Petkov wrote:
>> Haozhong Zhang wrote:
>>
>>> This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
>>> will be injected to only one VCPU rather than broadcast to all
>>> VCPUs. As KVM reports LMCE support on
On 06/07/16 17:10, Eduardo Habkost wrote:
> On Fri, Jun 03, 2016 at 02:09:43PM +0800, Haozhong Zhang wrote:
> [...]
> > +
> > +if (cpu->enable_lmce) {
> > +if (lmce_supported()) {
> > +cenv->mcg_cap |= MCG_LMCE_P;
> > +cenv->msr_ia32_feature_contr
On Fri, Jun 03, 2016 at 02:09:43PM +0800, Haozhong Zhang wrote:
[...]
> +
> +if (cpu->enable_lmce) {
> +if (lmce_supported()) {
> +cenv->mcg_cap |= MCG_LMCE_P;
> +cenv->msr_ia32_feature_control |=
> +MSR_IA32_FEATURE_CONTROL_LM
On 06/07/16 17:41, Haozhong Zhang wrote:
> On 06/04/16 18:03, Eduardo Habkost wrote:
> > On Sat, Jun 04, 2016 at 12:34:39PM +0200, Boris Petkov wrote:
> > > Haozhong Zhang wrote:
> > >
> > > >This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
> > > >will be injected to only on
On 06/04/16 18:03, Eduardo Habkost wrote:
> On Sat, Jun 04, 2016 at 12:34:39PM +0200, Boris Petkov wrote:
> > Haozhong Zhang wrote:
> >
> > >This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
> > >will be injected to only one VCPU rather than broadcast to all
> > >VCPUs. As KV
On Sat, Jun 04, 2016 at 12:34:39PM +0200, Boris Petkov wrote:
> Haozhong Zhang wrote:
>
> >This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
> >will be injected to only one VCPU rather than broadcast to all
> >VCPUs. As KVM reports LMCE support on Intel platforms, this featur
On 06/04/16 12:34, Boris Petkov wrote:
> Haozhong Zhang wrote:
>
> >This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
> >will be injected to only one VCPU rather than broadcast to all
> >VCPUs. As KVM reports LMCE support on Intel platforms, this features is
> >only available
On 06/04/16 12:15, Boris Petkov wrote:
> Haozhong Zhang wrote:
>
> >This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
> >will be injected to only one VCPU rather than broadcast to all
> >VCPUs. As KVM reports LMCE support on Intel platforms, this features is
> >only available
On 06/03/16 17:57, Radim Krčmář wrote:
> 2016-06-03 14:09+0800, Haozhong Zhang:
> > This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
> > will be injected to only one VCPU rather than broadcast to all
> > VCPUs. As KVM reports LMCE support on Intel platforms, this features is
>
Haozhong Zhang wrote:
>This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
>will be injected to only one VCPU rather than broadcast to all
>VCPUs. As KVM reports LMCE support on Intel platforms, this features is
>only available on Intel platforms.
>
>Signed-off-by: Ashok Raj
>
Haozhong Zhang wrote:
>This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
>will be injected to only one VCPU rather than broadcast to all
>VCPUs. As KVM reports LMCE support on Intel platforms, this features is
>only available on Intel platforms.
>
>Signed-off-by: Ashok Raj
>
2016-06-03 14:09+0800, Haozhong Zhang:
> This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
> will be injected to only one VCPU rather than broadcast to all
> VCPUs. As KVM reports LMCE support on Intel platforms, this features is
> only available on Intel platforms.
>
> Signed
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