Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180510220248.10272-1-...@kaod.org
Subject: [Qemu-devel] [PATCH v3] migration: discard non-migratable RAMBlocks
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(
* Cédric Le Goater (c...@kaod.org) wrote:
> On the POWER9 processor, the XIVE interrupt controller can control
> interrupt sources using MMIO to trigger events, to EOI or to turn off
> the sources. Priority management and interrupt acknowledgment is also
> controlled by MMIO in the presenter sub-en
On 05/11/2018 06:59 AM, Peter Xu wrote:
> On Fri, May 11, 2018 at 12:02:48AM +0200, Cédric Le Goater wrote:
>> On the POWER9 processor, the XIVE interrupt controller can control
>> interrupt sources using MMIO to trigger events, to EOI or to turn off
>> the sources. Priority management and interrup
Hello David,
Yesterday evening, I forgot to add the quote requested by Peter and
to add the MIPS maintainers.
Could you please add the paragraph below if the patch is accepted ?
I think it's worth resending a v4 for that.
Thanks,
C.
On 05/11/2018 12:02 AM, Cédric Le Goater wrote:
> On the PO
On Fri, May 11, 2018 at 12:02:48AM +0200, Cédric Le Goater wrote:
> On the POWER9 processor, the XIVE interrupt controller can control
> interrupt sources using MMIO to trigger events, to EOI or to turn off
> the sources. Priority management and interrupt acknowledgment is also
> controlled by MMIO
