On 10/27/2016 06:44 PM, Laszlo Ersek wrote:
On 10/27/16 13:27, Marcel Apfelbaum wrote:
On 10/14/2016 02:36 PM, Laszlo Ersek wrote:
On 10/13/16 16:05, Marcel Apfelbaum wrote:
On 10/13/2016 04:52 PM, Marcel Apfelbaum wrote:
+ -device
pci-bridge,id=pci_bridge1,bus=dmi_pci_bridge1[,chassis
On 10/27/16 13:27, Marcel Apfelbaum wrote:
> On 10/14/2016 02:36 PM, Laszlo Ersek wrote:
>> On 10/13/16 16:05, Marcel Apfelbaum wrote:
>>> On 10/13/2016 04:52 PM, Marcel Apfelbaum wrote:
+ -device
pci-bridge,id=pci_bridge1,bus=dmi_pci_bridge1[,chassis_nr=x][,addr=y]
\
+
On 10/17/2016 05:18 PM, Andrea Bolognani wrote:
On Thu, 2016-10-13 at 17:05 +0300, Marcel Apfelbaum wrote:
+PCI EXPRESS GUIDELINES
+==
+
+1. Introduction
+
+The doc proposes best practices on how to use PCI Express/PCI device
+in PCI Express based machines and
On 10/14/2016 02:36 PM, Laszlo Ersek wrote:
On 10/13/16 16:05, Marcel Apfelbaum wrote:
On 10/13/2016 04:52 PM, Marcel Apfelbaum wrote:
Proposes best practices on how to use PCI Express/PCI device
in PCI Express based machines and explain the reasoning behind them.
Signed-off-by: Marcel Apfelba
On 10/17/2016 05:07 PM, Laszlo Ersek wrote:
On 10/17/16 14:07, Gerd Hoffmann wrote:
Hi,
{26} Another remark (important to me) in this section: the document
doesn't state firmware expectations. It's clear the firmware is expected
to reserve no IO space for PCI Express Downstream Ports and Roo
On Mon, 2016-10-17 at 16:26 +0200, Laszlo Ersek wrote:
> > > > +2.1 Root Bus (pcie.0)
> > > > +=
> > > > +Place only the following kinds of devices directly on the Root Complex:
> > > > +(1) Devices with dedicated, specific functionality (network card,
> > > > +graph
On Thu, 2016-10-13 at 17:05 +0300, Marcel Apfelbaum wrote:
> > +PCI EXPRESS GUIDELINES
> > +==
> > +
> > +1. Introduction
> > +
> > +The doc proposes best practices on how to use PCI Express/PCI device
> > +in PCI Express based machines and explains the reasoning
On 10/17/16 14:07, Gerd Hoffmann wrote:
> Hi,
>
>> {26} Another remark (important to me) in this section: the document
>> doesn't state firmware expectations. It's clear the firmware is expected
>> to reserve no IO space for PCI Express Downstream Ports and Root Ports,
>> but what about MMIO?
>>
On 10/17/16 16:18, Andrea Bolognani wrote:
> On Thu, 2016-10-13 at 17:05 +0300, Marcel Apfelbaum wrote:
>>> +PCI EXPRESS GUIDELINES
>>> +==
>>> +
>>> +1. Introduction
>>> +
>>> +The doc proposes best practices on how to use PCI Express/PCI device
>>> +in PCI Expr
Hi,
> {26} Another remark (important to me) in this section: the document
> doesn't state firmware expectations. It's clear the firmware is expected
> to reserve no IO space for PCI Express Downstream Ports and Root Ports,
> but what about MMIO?
>
> We discussed this at length with Alex, but I
On 10/13/16 16:05, Marcel Apfelbaum wrote:
> On 10/13/2016 04:52 PM, Marcel Apfelbaum wrote:
>> Proposes best practices on how to use PCI Express/PCI device
>> in PCI Express based machines and explain the reasoning behind them.
>>
>> Signed-off-by: Marcel Apfelbaum
>> ---
>>
>> Hi,
>>
>> I am sen
On 10/13/2016 04:52 PM, Marcel Apfelbaum wrote:
Proposes best practices on how to use PCI Express/PCI device
in PCI Express based machines and explain the reasoning behind them.
Signed-off-by: Marcel Apfelbaum
---
Hi,
I am sending the doc twice, it appears the first time didn't make it to
q
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