On Wed, Mar 13, 2019 at 01:40:40PM +0100, Paolo Bonzini wrote:
> +static void tcg_out_endbr(TCGContext *s)
> +{
> +#if defined __CET__ && (__CET__ & 1)
Please include a comment explaining why __CET__ & 1 is necessary. Is
bit 0 of __CET__ the Indirect Branch Tracking feature flag?
signature.asc
On 14/03/19 16:15, Richard Henderson wrote:
> There's a cpuid bit though, leaf 7, ebx bit 20. If that's not set...
Yes, I can definitely test CPUID.
Paolo
On 3/14/19 3:50 AM, Paolo Bonzini wrote:
> There is a prctl to query the state, ARCH_X86_CET_STATUS, but I'm a bit
> wary of adding support for it before it hits the kernel; IBT only needs
> compiler support because the instructions/prefixes are a nop if
> disabled, unlike SHSTK which needs the "al
On 14/03/19 02:05, Richard Henderson wrote:
> On 3/13/19 5:40 AM, Paolo Bonzini wrote:
>> +static void tcg_out_endbr(TCGContext *s)
>> +{
>> +#if defined __CET__ && (__CET__ & 1)
>> +#ifdef __x86_64__
>> +tcg_out32(s, 0xfa1e0ff3);
>> +#else
>> +tcg_out32(s, 0xfb1e0ff3);
>> +#endif
>> +#endi
On 3/13/19 5:40 AM, Paolo Bonzini wrote:
> +static void tcg_out_endbr(TCGContext *s)
> +{
> +#if defined __CET__ && (__CET__ & 1)
> +#ifdef __x86_64__
> +tcg_out32(s, 0xfa1e0ff3);
> +#else
> +tcg_out32(s, 0xfb1e0ff3);
> +#endif
> +#endif
> +}
Normally we'd use a runtime test for the featur
On 3/13/19 5:40 AM, Paolo Bonzini wrote:
> Add endbr annotations before indirect branch targets. This lets QEMU enable
> IBT even for TCG-enabled builds.
> @@ -3514,6 +3526,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
>CPU_TEMP_BUF_NLONGS * sizeof(long));
>
>
