On Thu, Nov 25, 2010 at 11:18:26AM +0100, Gerd Hoffmann wrote:
> On 11/25/10 08:35, Alexander Graf wrote:
> >The way mmio endianness is currently implemented is horrifying.
> >
> >In the real world, CPUs have an endianness and write out data
> >to the memory bus. Instead of RAM, a receiving side he
On 11/25/10 08:35, Alexander Graf wrote:
The way mmio endianness is currently implemented is horrifying.
In the real world, CPUs have an endianness and write out data
to the memory bus. Instead of RAM, a receiving side here can be
a device. This device gets a byte stream again and needs to
make
On 25.11.2010, at 11:18, Gerd Hoffmann wrote:
> On 11/25/10 08:35, Alexander Graf wrote:
>> The way mmio endianness is currently implemented is horrifying.
>>
>> In the real world, CPUs have an endianness and write out data
>> to the memory bus. Instead of RAM, a receiving side here can be
>> a
