Re: [PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg

在 2022/7/28 下午2:41, Mayuresh Chitale 写道: On Fri, 2022-07-22 at 08:45 +0800, Weiwei Li wrote: 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: Accesses to henvcfg, henvcfgh and senvcfg are allowed only if corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is ge

Re: [PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg

On Fri, 2022-07-22 at 08:45 +0800, Weiwei Li wrote: > 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: > > Accesses to henvcfg, henvcfgh and senvcfg are allowed only if > > corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an > > illegal instruction trap is generated. > > > > Signed-off-by:

Re: [PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg

在 2022/7/21 下午11:31, Mayuresh Chitale 写道: Accesses to henvcfg, henvcfgh and senvcfg are allowed only if corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 100 +