Hi David, All,
I am revisiting/reviving this patch.
On 5/5/21 11:20, David Gibson wrote:
On Wed, Apr 21, 2021 at 11:50:40AM +0530, Ravi Bangoria wrote:
Hi David,
On 4/19/21 10:23 AM, David Gibson wrote:
On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
Since we have released
On Wed, Apr 21, 2021 at 11:50:40AM +0530, Ravi Bangoria wrote:
> Hi David,
>
> On 4/19/21 10:23 AM, David Gibson wrote:
> > On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
> > > As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> > > availability of 2nd DAWR regist
On 4/21/21 6:56 PM, David Gibson wrote:
I don't actually know if qemu has TCG watchpoint support on any
hardware. Presumably it would mean instrumenting all the tcg loads
and stores.
We tag the soft tlb for pages that contain watchpoints.
See include/hw/core/cpu.h:
cpu_watchpoint_insert
c
On Wed, Apr 21, 2021 at 12:24:22PM +0530, Ravi Bangoria wrote:
> Hi Cedric,
>
> On 4/21/21 12:01 PM, Cédric Le Goater wrote:
> > On 4/21/21 8:20 AM, Ravi Bangoria wrote:
> > > Hi David,
> > >
> > > On 4/19/21 10:23 AM, David Gibson wrote:
> > > > On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Ban
Hi Cedric,
On 4/21/21 12:01 PM, Cédric Le Goater wrote:
On 4/21/21 8:20 AM, Ravi Bangoria wrote:
Hi David,
On 4/19/21 10:23 AM, David Gibson wrote:
On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
As per the PAPR, bit 0 of byte 64 in pa-features property indicates
availability
On 4/21/21 8:20 AM, Ravi Bangoria wrote:
> Hi David,
>
> On 4/19/21 10:23 AM, David Gibson wrote:
>> On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
>>> As per the PAPR, bit 0 of byte 64 in pa-features property indicates
>>> availability of 2nd DAWR registers. i.e. If this bit is se
Hi David,
On 4/19/21 10:23 AM, David Gibson wrote:
On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
As per the PAPR, bit 0 of byte 64 in pa-features property indicates
availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
DAWR is present, otherwise not. Use KVM_CAP_PPC_
On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
> As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to
> find whether kvm supports 2
On 4/12/21 1:44 PM, Ravi Bangoria wrote:
> As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to
> find whether kvm supports 2nd DAWR or not. If it'
