Re: [PATCH v5 2/4] target/riscv: implementation-defined constant parameters

2020-02-27 Thread Richard Henderson
On 2/21/20 1:45 AM, LIU Zhiwei wrote: > vlen is the vector register length in bits. > elen is the max element size in bits. > vext_spec is the vector specification version, default value is v0.7.1. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/cpu.c | 7 +++ > target/riscv/cpu.h | 5 +++

Re: [PATCH v5 2/4] target/riscv: implementation-defined constant parameters

2020-02-26 Thread Alistair Francis
On Fri, Feb 21, 2020 at 1:45 AM LIU Zhiwei wrote: > > vlen is the vector register length in bits. > elen is the max element size in bits. > vext_spec is the vector specification version, default value is v0.7.1. > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > tar