Zhang, Qi1
> > > Cc: qemu-devel@nongnu.org; ehabk...@redhat.com; m...@redhat.com;
> > > pbonz...@redhat.com; r...@twiddle.net; Qi, Yadong
> > > Subject: Re: [PATCH V2] intel_iommu: TM field should not be in reserved
> > > bits
> > >
> > > On
t; > Cc: qemu-devel@nongnu.org; ehabk...@redhat.com; m...@redhat.com;
> > > pbonz...@redhat.com; r...@twiddle.net; Qi, Yadong
> > >
> > > Subject: Re: [PATCH V2] intel_iommu: TM field should not be in
> > > reserved bits
> > >
> > > On Fri, Sep 27,
pbonz...@redhat.com; r...@twiddle.net; Qi, Yadong
> > Subject: Re: [PATCH V2] intel_iommu: TM field should not be in reserved bits
> >
> > On Fri, Sep 27, 2019 at 08:03:21AM +, Zhang, Qi1 wrote:
> > >
> > >
> > > > -Original Message-
>
t; > Cc: qemu-devel@nongnu.org; ehabk...@redhat.com; m...@redhat.com;
> > > pbonz...@redhat.com; r...@twiddle.net
> > > Subject: Re: [PATCH V2] intel_iommu: TM field should not be in
> > > reserved bits
> > >
> > > On Fri, Sep 27, 2019 at 12:58:38PM +08
Patchew URL: https://patchew.org/QEMU/20190927045838.2968-1-qi1.zh...@intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190927045838.2968-1-qi1.zh...@intel.com
Subject: [PATCH V2] intel_iommu: TM field should
On Fri, Sep 27, 2019 at 12:58:38PM +0800, qi1.zh...@intel.com wrote:
> From: "Zhang, Qi"
>
> When dt is supported, TM field should not be Reserved(0).
>
> Refer to VT-d Spec 9.8
>
> Signed-off-by: Zhang, Qi
> Signed-off-by: Qi, Yadong
> ---
> hw/i386/intel_iommu.c | 12 ++--
> pbonz...@redhat.com; r...@twiddle.net
> > Subject: Re: [PATCH V2] intel_iommu: TM field should not be in reserved bits
> >
> > On Fri, Sep 27, 2019 at 12:58:38PM +0800, qi1.zh...@intel.com wrote:
> > > From: "Zhang, Qi"
> > >
> >
> -Original Message-
> From: Peter Xu
> Sent: Friday, September 27, 2019 2:10 PM
> To: Zhang, Qi1
> Cc: qemu-devel@nongnu.org; ehabk...@redhat.com; m...@redhat.com;
> pbonz...@redhat.com; r...@twiddle.net
> Subject: Re: [PATCH V2] intel_iommu: TM field should no
On Fri, Sep 27, 2019 at 12:58:38PM +0800, qi1.zh...@intel.com wrote:
> From: "Zhang, Qi"
>
> When dt is supported, TM field should not be Reserved(0).
>
> Refer to VT-d Spec 9.8
>
> Signed-off-by: Zhang, Qi
> Signed-off-by: Qi, Yadong
> ---
> hw/i386/intel_iommu.c | 12 ++--
