On 8/27/20 3:08 AM, Edgar E. Iglesias wrote:
>> Ok. I assume this follows a write to something like an interrupt controller
>> register?
>
> yes, kind of. It's a memory store to a device that raises an interrupt as a
> result of that store. The interrupt propagates to the CPU and on real HW if
>
On Thu, Aug 27, 2020 at 02:58:06AM -0700, Richard Henderson wrote:
> On 8/27/20 2:24 AM, Edgar E. Iglesias wrote:
> >> +/*
> >> + * Instruction access memory barrier.
> >> + * End the TB so that we recognize self-modified code immediately.
> >> + */
> >> +if (mbar_imm & 1) {
> >
On 8/27/20 2:24 AM, Edgar E. Iglesias wrote:
>> +/*
>> + * Instruction access memory barrier.
>> + * End the TB so that we recognize self-modified code immediately.
>> + */
>> +if (mbar_imm & 1) {
>> +dc->cpustate_changed = 1;
>> +}
>
> This should be (mbar_imm & 1)
On Tue, Aug 25, 2020 at 01:59:37PM -0700, Richard Henderson wrote:
> Split this out of the normal branch instructions, as it requires
> special handling. End the TB only for an instruction barrier.
>
> Signed-off-by: Richard Henderson
> ---
> target/microblaze/insns.decode | 2 +
> target/micr
