On 1/8/22 01:39, Peter Maydell wrote:
(1) The handling of the BaseADDR field for TLB range
invalidates needs updating (there's a TODO to this effect in
tlbi_aa64_range_get_base()).
Side note: in that function, we shift the field by TARGET_PAGE_BITS,
but the docs say that the shift should depend
On Wed, 8 Dec 2021 at 23:21, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Again, a commit message would be nice.
> ---
> target/arm/cpu.h | 12 +++
> target/arm/internals.h | 2 ++
> target/arm/cpu64.c | 2 ++
> target/arm/helper.c| 80 +
On 12/14/21 6:57 AM, Alex Bennée wrote:
+static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
+{
+return sextract64(id->id_aa64mmfr0,
+ R_ID_AA64MMFR0_TGRAN4_SHIFT,
+ R_ID_AA64MMFR0_TGRAN4_LENGTH) >= 1;
Is this correct - it sh
Richard Henderson writes:
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 12 +++
> target/arm/internals.h | 2 ++
> target/arm/cpu64.c | 2 ++
> target/arm/helper.c| 80 +++---
> 4 files changed, 83 insertions(+), 13 delet
