On 2/2/20 1:29 PM, Peter Maydell wrote:
> Yes, but SPSR_ELx isn't started with a clean zero and built up
> the way the new PSTATE is, it gets copied from the AArch32 CPSR
> via cpsr_read(). I forget how carefully we keep the guest from setting
> CPSR bits that aren't really valid for the CPU...
We
On Sun, 2 Feb 2020 at 01:00, Richard Henderson
wrote:
> > Does the "on exception entry PSTATE.UAO is zeroed" behaviour
> > fall out automatically for us?
>
> Yes, aarch64_pstate_mode() returns a clean PSTATE.
>
> > How about "on exception entry
> > from aarch32 to aarch64 SPSR_ELx.UAO is set to ze
On 12/6/19 10:30 AM, Peter Maydell wrote:
>> +if (cpu_isar_feature(aa64_uao, cpu)) {
>> +static const ARMCPRegInfo uao_reginfo[] = {
>> +{ .name = "UAO", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4,
>> + .typ
On Tue, 3 Dec 2019 at 23:42, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 6 ++
> target/arm/helper.c| 21 +
> target/arm/translate-a64.c | 14 ++
> 3 files changed, 41 insertions(+)
>
> diff --git
On 12/6/19 10:30 AM, Peter Maydell wrote:
>> +if (cpu_isar_feature(aa64_uao, cpu)) {
>> +static const ARMCPRegInfo uao_reginfo[] = {
>> +{ .name = "UAO", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4,
>> + .typ
