On 29/08/2021 14:17, Peter Maydell wrote:
On Sun, 29 Aug 2021 at 11:07, Mark Cave-Ayland
wrote:
According to the "Z80X30 Register Reset Values" table in the ESCC datasheet
bits 2 and 6 are set whilst bits 0 and 1 are cleared during channel reset.
All other bits should be left unaltered.
Sign
On Sun, 29 Aug 2021 at 11:07, Mark Cave-Ayland
wrote:
>
> According to the "Z80X30 Register Reset Values" table in the ESCC datasheet
> bits 2 and 6 are set whilst bits 0 and 1 are cleared during channel reset.
> All other bits should be left unaltered.
>
> Signed-off-by: Mark Cave-Ayland
> ---
>
