: Re: [PATCH 2/2] hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in
> IRQ calculation
>
> On 1/11/24 17:11, Peter Maydell wrote:
> > When calculating the index into the GIC's GPIO array for per-CPU
> > interrupts, we have to start with the number of SPIs. The code
> >
On 1/11/24 17:11, Peter Maydell wrote:
When calculating the index into the GIC's GPIO array for per-CPU
interrupts, we have to start with the number of SPIs. The code
currently hard-codes this to 'NUM_IRQS = 256'. However the number of
SPIs is set separately and implicitly by the value of
AST27
On 1/11/24 13:11, Peter Maydell wrote:
When calculating the index into the GIC's GPIO array for per-CPU
interrupts, we have to start with the number of SPIs. The code
currently hard-codes this to 'NUM_IRQS = 256'. However the number of
SPIs is set separately and implicitly by the value of
AST27
On 11/1/24 09:11, Peter Maydell wrote:
When calculating the index into the GIC's GPIO array for per-CPU
interrupts, we have to start with the number of SPIs. The code
currently hard-codes this to 'NUM_IRQS = 256'. However the number of
SPIs is set separately and implicitly by the value of
AS
