RE: [PATCH] target/riscv: raise exception to HS-mode at get_physical_address

2020-10-09 Thread Jiangyifei
ann > ; Zhangxiaofeng (F) > ; Alistair Francis > ; yinyipeng ; Palmer > Dabbelt ; Wubin (H) ; > dengkai (A) > Subject: Re: [PATCH] target/riscv: raise exception to HS-mode at > get_physical_address > > On Sun, Sep 27, 2020 at 12:54 AM Jiangyifei wrote: > > > > &g

Re: [PATCH] target/riscv: raise exception to HS-mode at get_physical_address

2020-09-30 Thread Alistair Francis
; open > > list:RISC-V ; Zhanghailiang > > ; Sagar Karandikar > > ; Bastian Koppelmann > > ; Zhangxiaofeng (F) > > ; Alistair Francis > > ; yinyipeng ; Palmer > > Dabbelt ; Wubin (H) ; > > dengkai (A) > > Subject: Re: [PATCH] target/riscv: raise e

RE: [PATCH] target/riscv: raise exception to HS-mode at get_physical_address

2020-09-27 Thread Jiangyifei
ann > ; Zhangxiaofeng (F) > ; Alistair Francis > ; yinyipeng ; Palmer > Dabbelt ; Wubin (H) ; > dengkai (A) > Subject: Re: [PATCH] target/riscv: raise exception to HS-mode at > get_physical_address > > On Mon, Aug 24, 2020 at 1:43 AM Yifei Jiang wrote: > > > > VS-s

Re: [PATCH] target/riscv: raise exception to HS-mode at get_physical_address

2020-09-25 Thread Alistair Francis
On Mon, Aug 24, 2020 at 1:43 AM Yifei Jiang wrote: > > VS-stage translation at get_physical_address needs to translate pte > address by G-stage translation. But the G-stage translation error > can not be distinguished from VS-stage translation error in > riscv_cpu_tlb_fill. On migration, destinati