On Sun, Sep 26, 2021 at 10:49:53AM +0800, Bin Meng wrote:
> On Sat, Sep 18, 2021 at 12:19 PM Guenter Roeck wrote:
> >
> > On 9/17/21 8:09 PM, Cheng, Xuzhou wrote:
> > >>> I got some free time in the past days to investigate this issue.
> > >>> Guenter is right, the Linux imx-spi driver does not w
On Sat, Sep 18, 2021 at 12:19 PM Guenter Roeck wrote:
>
> On 9/17/21 8:09 PM, Cheng, Xuzhou wrote:
> >>> I got some free time in the past days to investigate this issue. Guenter
> >>> is right, the Linux imx-spi driver does not work on QEMU.
> >>>
> >>> The reason is that the state of m25p80 mach
On 9/17/21 8:09 PM, Cheng, Xuzhou wrote:
I got some free time in the past days to investigate this issue. Guenter is
right, the Linux imx-spi driver does not work on QEMU.
The reason is that the state of m25p80 machine loops in STATE_READING_DATA
state after receiving RDSR command, the new com
> > I got some free time in the past days to investigate this issue. Guenter is
> > right, the Linux imx-spi driver does not work on QEMU.
> >
> > The reason is that the state of m25p80 machine loops in STATE_READING_DATA
> > state after receiving RDSR command, the new command is ignored. Before
On Thu, Sep 16, 2021 at 10:21:16AM +, Cheng, Xuzhou wrote:
> > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
> > index 189423bb3a..7a093156bd 100644
> > --- a/hw/ssi/imx_spi.c
> > +++ b/hw/ssi/imx_spi.c
> > @@ -167,6 +167,8 @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
> > DPRINT
> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
> index 189423bb3a..7a093156bd 100644
> --- a/hw/ssi/imx_spi.c
> +++ b/hw/ssi/imx_spi.c
> @@ -167,6 +167,8 @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
> DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n",
> fifo32_nu
On 9/8/21 2:05 AM, Cheng, Xuzhou wrote:
Thanks Bin added me into this loop.
Hi, Guenter
I am interested in your patch and the issue what you found. I want to reproduce
your issue on Linux, but I failed, the spi-nor of sabrelite on Linux does not
work.
Could you share your Linux kernel versio
hieu-Daudé ; Peter Maydell
; Alistair Francis ; QEMU
Developers ; qemu-arm ;
Jean-Christophe Dubois
Subject: Re: [PATCH] hw/ssi: imx_spi: Improve chip select handling
[Please note: This e-mail is from an EXTERNAL e-mail address]
On Wed, Sep 8, 2021 at 2:29 PM Bin Meng wrote:
>
> On Sun,
On Wed, Sep 8, 2021 at 2:29 PM Bin Meng wrote:
>
> On Sun, Sep 5, 2021 at 10:08 AM Guenter Roeck wrote:
> >
> > On 9/4/21 4:19 PM, Philippe Mathieu-Daudé wrote:
> > > On 9/5/21 1:06 AM, Bin Meng wrote:
> > >> On Sun, Sep 5, 2021 at 1:13 AM Guenter Roeck wrote:
> > >>>
> > >>> On 9/2/21 12:29 PM,
On Sun, Sep 5, 2021 at 10:08 AM Guenter Roeck wrote:
>
> On 9/4/21 4:19 PM, Philippe Mathieu-Daudé wrote:
> > On 9/5/21 1:06 AM, Bin Meng wrote:
> >> On Sun, Sep 5, 2021 at 1:13 AM Guenter Roeck wrote:
> >>>
> >>> On 9/2/21 12:29 PM, Peter Maydell wrote:
> On Thu, 2 Sept 2021 at 17:09, Guent
On 9/4/21 4:19 PM, Philippe Mathieu-Daudé wrote:
On 9/5/21 1:06 AM, Bin Meng wrote:
On Sun, Sep 5, 2021 at 1:13 AM Guenter Roeck wrote:
On 9/2/21 12:29 PM, Peter Maydell wrote:
On Thu, 2 Sept 2021 at 17:09, Guenter Roeck wrote:
On 9/2/21 8:58 AM, Peter Maydell wrote:
On Sun, 8 Aug 2021 a
On 9/4/21 4:06 PM, Bin Meng wrote:
On Sun, Sep 5, 2021 at 1:13 AM Guenter Roeck wrote:
On 9/2/21 12:29 PM, Peter Maydell wrote:
On Thu, 2 Sept 2021 at 17:09, Guenter Roeck wrote:
On 9/2/21 8:58 AM, Peter Maydell wrote:
On Sun, 8 Aug 2021 at 02:34, Guenter Roeck wrote:
The control regis
On 9/5/21 1:06 AM, Bin Meng wrote:
> On Sun, Sep 5, 2021 at 1:13 AM Guenter Roeck wrote:
>>
>> On 9/2/21 12:29 PM, Peter Maydell wrote:
>>> On Thu, 2 Sept 2021 at 17:09, Guenter Roeck wrote:
On 9/2/21 8:58 AM, Peter Maydell wrote:
> On Sun, 8 Aug 2021 at 02:34, Guenter Roeck wrote:
On Sun, Sep 5, 2021 at 1:13 AM Guenter Roeck wrote:
>
> On 9/2/21 12:29 PM, Peter Maydell wrote:
> > On Thu, 2 Sept 2021 at 17:09, Guenter Roeck wrote:
> >>
> >> On 9/2/21 8:58 AM, Peter Maydell wrote:
> >>> On Sun, 8 Aug 2021 at 02:34, Guenter Roeck wrote:
>
> The control register doe
On 9/2/21 12:29 PM, Peter Maydell wrote:
On Thu, 2 Sept 2021 at 17:09, Guenter Roeck wrote:
On 9/2/21 8:58 AM, Peter Maydell wrote:
On Sun, 8 Aug 2021 at 02:34, Guenter Roeck wrote:
The control register does not really have a means to deselect
all chip selects directly. As result, CS is ef
On Thu, 2 Sept 2021 at 17:09, Guenter Roeck wrote:
>
> On 9/2/21 8:58 AM, Peter Maydell wrote:
> > On Sun, 8 Aug 2021 at 02:34, Guenter Roeck wrote:
> >>
> >> The control register does not really have a means to deselect
> >> all chip selects directly. As result, CS is effectively never
> >> dese
On 9/2/21 8:58 AM, Peter Maydell wrote:
On Sun, 8 Aug 2021 at 02:34, Guenter Roeck wrote:
The control register does not really have a means to deselect
all chip selects directly. As result, CS is effectively never
deselected, and connected flash chips fail to perform read
operations since they
On Sun, 8 Aug 2021 at 02:34, Guenter Roeck wrote:
>
> The control register does not really have a means to deselect
> all chip selects directly. As result, CS is effectively never
> deselected, and connected flash chips fail to perform read
> operations since they don't get the expected chip selec
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