post (which
describes exactly my problem. Thank you for finding that!)
-Original Message-
From: Philippe Mathieu-Daudé
Sent: Friday, December 13, 2019 8:39 PM
To: Bensch, Alexander ; qemu-devel@nongnu.org
Cc: Peter Maydell ; Richard Henderson
Subject: [EXTERNAL] Re: MIPS cache bypass on c
Hi Alexander,
On 12/13/19 7:59 PM, Bensch, Alexander wrote:
Hi all,
Currently stuck on a problem in QEMU 4.0.0. I’m trying to implement a
custom device using a MIPS 24Kc CPU. The device boots from an SPI flash
device that is mapped to 0x9F00 (physical address 0x1F00). I got
the initi
Sensitive
Hi all,
Currently stuck on a problem in QEMU 4.0.0. I'm trying to implement a custom
device using a MIPS 24Kc CPU. The device boots from an SPI flash device that is
mapped to 0x9F00 (physical address 0x1F00). I got the initial load and
execute working by direct loading a flas
