Re: [RFC v4 69/70] target/riscv: gdb: support vector registers for rv64

On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote: > +++ b/gdb-xml/riscv-64bit-csr.xml > @@ -248,4 +248,11 @@ > > > > + > + > + > + > + > + > + Just because these are csr's doesn't mean they're unrelated to RVV. I would think that ideally they would be in the (generated)

[RFC v4 69/70] target/riscv: gdb: support vector registers for rv64

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Frank Chang --- gdb-xml/riscv-64bit-csr.xml | 7 ++ target/riscv/cpu.c | 1 + target/riscv/cpu.h | 25 +++ target/riscv/gdbstub.c | 126 +++- 4 files changed, 157 i