> From: David Gibson < da...@gibson.dropbear.id.au >
> Sent: Friday, February 14, 2020 1:36 PM
> To: Liu, Yi L
> Subject: Re: [RFC v3 03/25] hw/iommu: introduce IOMMUContext
>
> On Wed, Feb 12, 2020 at 07:15:13AM +, Liu, Yi L wrote:
> > Hi Peter,
> &
On Wed, Feb 12, 2020 at 07:15:13AM +, Liu, Yi L wrote:
> Hi Peter,
>
> > From: Peter Xu
> > Sent: Wednesday, February 12, 2020 12:59 AM
> > To: Liu, Yi L
> > Subject: Re: [RFC v3 03/25] hw/iommu: introduce IOMMUContext
> >
> > On Fri, Jan 31,
> From: Peter Xu
> Sent: Thursday, February 13, 2020 12:00 AM
> To: Liu, Yi L
> Subject: Re: [RFC v3 03/25] hw/iommu: introduce IOMMUContext
>
> On Wed, Feb 12, 2020 at 07:15:13AM +, Liu, Yi L wrote:
>
> [...]
>
> > While considering your suggestion on
On Wed, Feb 12, 2020 at 07:15:13AM +, Liu, Yi L wrote:
[...]
> While considering your suggestion on dropping one of the two abstract
> layers. I came up a new proposal as below:
>
> We may drop the IOMMUContext in this series, and rename DualStageIOMMUObject
> to HostIOMMUContext, which is p
Hi Peter,
> From: Peter Xu
> Sent: Wednesday, February 12, 2020 12:59 AM
> To: Liu, Yi L
> Subject: Re: [RFC v3 03/25] hw/iommu: introduce IOMMUContext
>
> On Fri, Jan 31, 2020 at 11:42:13AM +, Liu, Yi L wrote:
> > > I'm not very clear on the relations
On Fri, Jan 31, 2020 at 11:42:13AM +, Liu, Yi L wrote:
> > I'm not very clear on the relationship betwen an IOMMUContext and a
> > DualStageIOMMUObject. Can there be many IOMMUContexts to a
> > DualStageIOMMUOBject? The other way around? Or is it just
> > zero-or-one DualStageIOMMUObjects to
Hi David,
> From: David Gibson [mailto:da...@gibson.dropbear.id.au]
> Sent: Friday, January 31, 2020 12:07 PM
> To: Liu, Yi L
> Subject: Re: [RFC v3 03/25] hw/iommu: introduce IOMMUContext
>
> On Wed, Jan 29, 2020 at 04:16:34AM -0800, Liu, Yi L wrote:
> > From: Peter Xu
On Wed, Jan 29, 2020 at 04:16:34AM -0800, Liu, Yi L wrote:
> From: Peter Xu
>
> Currently, many platform vendors provide the capability of dual stage
> DMA address translation in hardware. For example, nested translation
> on Intel VT-d scalable mode, nested stage translation on ARM SMMUv3,
> and
From: Peter Xu
Currently, many platform vendors provide the capability of dual stage
DMA address translation in hardware. For example, nested translation
on Intel VT-d scalable mode, nested stage translation on ARM SMMUv3,
and etc. Also there are efforts to make QEMU vIOMMU be backed by dual
stag
