Re: [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register

On 7/22/20 2:15 AM, frank.ch...@sifive.com wrote: > From: LIU Zhiwei > > Signed-off-by: LIU Zhiwei > Signed-off-by: Frank Chang > --- > target/riscv/cpu_bits.h | 7 +++ > target/riscv/csr.c | 21 + > 2 files changed, 28 insertions(+) Reviewed-by: Richard Henderso

[RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 21 + 2 files changed, 28 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5b0be0bb88..7afdd4814b 100