On Fri, Aug 6, 2021 at 7:51 PM Bin Meng wrote:
>
> On Fri, Aug 6, 2021 at 2:12 PM Ruinland Chuan-Tzu Tsa(蔡傳資)
> wrote:
> >
> > Hi Bin and Alistair,
> >
> > >> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without
> >
> > > The latest RISC-V core from Andes is AX45 and A45. Should we ju
On Fri, Aug 6, 2021 at 2:12 PM Ruinland Chuan-Tzu Tsa(蔡傳資)
wrote:
>
> Hi Bin and Alistair,
>
> >> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without
>
> > The latest RISC-V core from Andes is AX45 and A45. Should we just
> > support the latest one?
>
> Maybe we can have them all ?
>
Hi Bin and Alistair,
>> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without
> The latest RISC-V core from Andes is AX45 and A45. Should we just
> support the latest one?
Maybe we can have them all ?
AX25 and A25 is still in production, and we still have new clients using these
CPU
On Fri, Aug 6, 2021 at 2:00 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> From: Ruinalnd ChuanTzu Tsai
>
> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without
The latest RISC-V core from Andes is AX45 and A45. Should we just
support the latest one?
> enhanced features (yet).
>
> Signed-off
From: Ruinalnd ChuanTzu Tsai
Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without
enhanced features (yet).
Signed-off-by: Dylan Jhong
---
target/riscv/cpu.c | 16
target/riscv/cpu.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/target/riscv/cpu.c b/targe
