Re: [RFC PATCH v3 1/2] target/riscv: Add RISC-V CSR qtest support

On 25/06/2024 17.35, Ivan Klokov wrote: The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov --- tar

[RFC PATCH v3 1/2] target/riscv: Add RISC-V CSR qtest support

The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov --- target/riscv/cpu.c | 14 +++ targe