On 3/26/22 14:04, Richard Henderson wrote:
On 3/24/22 13:08, Leandro Lupori wrote:
+ /* Processor Attention */
+ POWERPC_EXCP_ATTN = 0x100,
+ /*
+ * NOTE: POWERPC_EXCP_ATTN uses values from 0x100 to 0x1ff to return
+ *
On 3/24/22 13:08, Leandro Lupori wrote:
+/* Processor Attention */
+POWERPC_EXCP_ATTN = 0x100,
+/*
+ * NOTE: POWERPC_EXCP_ATTN uses values from 0x100 to 0x1ff to return
+ * error codes.
+ */
As used below,
On Fri, Mar 25, 2022 at 12:11:47PM -0300, Fabiano Rosas wrote:
> Leandro Lupori writes:
>
> > From: Cédric Le Goater
> >
> > Check the HID0 bit to send signal, currently modeled as a checkstop.
> > The QEMU implementation adds an exit using the GPR[3] value (that's a
> > hack for tests)
> >
> >
Leandro Lupori writes:
> From: Cédric Le Goater
>
> Check the HID0 bit to send signal, currently modeled as a checkstop.
> The QEMU implementation adds an exit using the GPR[3] value (that's a
> hack for tests)
>
> Signed-off-by: Cédric Le Goater
> Signed-off-by: Leandro Lupori
> ---
> target
From: Cédric Le Goater
Check the HID0 bit to send signal, currently modeled as a checkstop.
The QEMU implementation adds an exit using the GPR[3] value (that's a
hack for tests)
Signed-off-by: Cédric Le Goater
Signed-off-by: Leandro Lupori
---
target/ppc/cpu.h | 8
target/pp
