On Tue, 7 Jan 2020 at 21:37, Beata Michalska wrote:
>
> On Tue, 7 Jan 2020 at 14:28, Peter Maydell wrote:
> > Another thing that occurred to me last night -- why do we need
> > to do this adjustment of the PC/r15 ? If this is the kernel
> > handing control to userspace to say "this is not an inst
On Tue, 7 Jan 2020 at 14:28, Peter Maydell wrote:
>
> On Fri, 20 Dec 2019 at 20:27, Beata Michalska
> wrote:
> >
> > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> > exception with no valid ISS info to be decoded. The lack of decode info
> > makes it at least tricky to
On Fri, 20 Dec 2019 at 20:27, Beata Michalska
wrote:
>
> On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> exception with no valid ISS info to be decoded. The lack of decode info
> makes it at least tricky to emulate those instruction which is one of the
> (many) reasons w
On Mon, 6 Jan 2020 at 17:15, Peter Maydell wrote:
>
> On Fri, 20 Dec 2019 at 20:27, Beata Michalska
> wrote:
> >
> > On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> > exception with no valid ISS info to be decoded. The lack of decode info
> > makes it at least tricky to
On Fri, 20 Dec 2019 at 20:27, Beata Michalska
wrote:
>
> On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
> exception with no valid ISS info to be decoded. The lack of decode info
> makes it at least tricky to emulate those instruction which is one of the
> (many) reasons w
On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
exception with no valid ISS info to be decoded. The lack of decode info
makes it at least tricky to emulate those instruction which is one of the
(many) reasons why KVM will not even try to do so.
Add suport for handling thos
