Re: [RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode

2021-06-28 Thread LIU Zhiwei
On 2021/6/26 下午11:31, Frank Chang wrote: LIU Zhiwei mailto:zhiwei_...@c-sky.com>> 於 2021年4月9日 週五 下午3:52寫道: The machine mode mclicbase CSR is an XLEN-bit read-only register providing the base address of CLIC memory mapped registers. Signed-off-by: LIU Zhiwei mailto:zhiwei_...@c

Re: [RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode

2021-06-26 Thread Frank Chang
LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道: > The machine mode mclicbase CSR is an XLEN-bit read-only register providing > the base address of CLIC memory mapped registers. > > Signed-off-by: LIU Zhiwei > --- > hw/intc/riscv_clic.c | 1 + > target/riscv/cpu.h | 1 + > 2 files changed, 2 insertions(+)

[RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode

2021-04-09 Thread LIU Zhiwei
The machine mode mclicbase CSR is an XLEN-bit read-only register providing the base address of CLIC memory mapped registers. Signed-off-by: LIU Zhiwei --- hw/intc/riscv_clic.c | 1 + target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/intc/riscv_clic.c b/hw/intc/riscv_c