Re: [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction

2021-08-09 Thread LIU Zhiwei
On 2021/8/6 上午6:17, Richard Henderson wrote: On 8/4/21 4:53 PM, LIU Zhiwei wrote:   static bool trans_srli(DisasContext *ctx, arg_srli *a)   { +    if (ctx->uxl32) { +    return trans_srliw(ctx, a); +    }   return gen_shifti(ctx, a, tcg_gen_shr_tl);   } First, trans_srliw begins wit

Re: [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction

2021-08-05 Thread Richard Henderson
On 8/4/21 4:53 PM, LIU Zhiwei wrote: static bool trans_srli(DisasContext *ctx, arg_srli *a) { +if (ctx->uxl32) { +return trans_srliw(ctx, a); +} return gen_shifti(ctx, a, tcg_gen_shr_tl); } First, trans_srliw begins with REQUIRE_64BIT, which *should* fail when RV32 i

[RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction

2021-08-04 Thread LIU Zhiwei
Reuse 32-bit right shift instructions. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvi.c.inc | 12 1 file changed, 12 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 6201c07795..698a28731e 100644 --