Re: [RFC 09/65] target/riscv: rvv-0.9: add vlenb register

2020-07-10 Thread Richard Henderson
On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote: > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 228b9bdb5d..871c2ddfa1 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -317,6 +317,7 @@ static void riscv_cpu_reset(DeviceState *dev) > env->mstatus &= ~(MSTATUS_M

[RFC 09/65] target/riscv: rvv-0.9: add vlenb register

2020-07-10 Thread frank . chang
From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++ 4 files changed, 10 insertions(+) diff --git a/target/riscv/