Re: [RFC 06/65] target/riscv: rvv-0.9: add vcsr register

2020-07-10 Thread Richard Henderson
On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote: > +[CSR_VCSR] ={ vs, read_vcsr,write_vcsr > }, As long as you have the vext_spec argument, you need a separate vs_0_9 predicate function, so that this csr is not available to VEXT_VERSION_0_07_1. r~

[RFC 06/65] target/riscv: rvv-0.9: add vcsr register

2020-07-10 Thread frank . chang
From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 21 + 2 files changed, 28 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8117e8b5a7..202440e5eb 100