Re: [RESEND] target/riscv: fix RV128 lq encoding

2022-01-20 Thread Christoph Müllner
Hi Frédéric, you are right, I misunderstood the "LQ is added to the MISC-MEM major opcode" part of the spec. I saw the encoding conflict with the CBO instructions and thought of a bug in qemu's LQ encoding. Philipp already highlighted that cbo.* instructions are actually LQ with rd=0. Thanks, Chr

Re: [RESEND] target/riscv: fix RV128 lq encoding

2022-01-19 Thread Philipp Tomsich
The cbo.* mnemonics share their opcode space with lq for those cases where rd == 0 ("brownfield" encodings). "Major opcode" refers to inst[6:0] according to chapter 26. In overlapping multi-group syntax, this would look like: > { > > # *** RV32 Zicbom Standard Extension *** > > cbo_clean 000

Re: [RESEND] target/riscv: fix RV128 lq encoding

2022-01-19 Thread Frédéric Pétrot
Le 18/01/2022 à 17:32, Christoph Muellner a écrit : If LQ has func3==010 and is located in the MISC-MEM opcodes, then it conflicts with the CBO opcode space. However, since LQ is specified as: "LQ is added to the MISC-MEM major opcode", we have an implementation bug, because 'major opcode' refers

[RESEND] target/riscv: fix RV128 lq encoding

2022-01-18 Thread Christoph Muellner
If LQ has func3==010 and is located in the MISC-MEM opcodes, then it conflicts with the CBO opcode space. However, since LQ is specified as: "LQ is added to the MISC-MEM major opcode", we have an implementation bug, because 'major opcode' refers to func3, which must be 111. This results in the fol