On 13/02/18 21:01, Steven Seeger wrote:
Consider the following code:
0x100 cmp %g5, 3
0x104 be 0x200
0x108 b 0x300
I believe this is what is described on page 55 of the sparc v8 manual as
unpredictable behavior, where a Bicc precedes an unconditional branch.
QEMU actually crashes
Consider the following code:
0x100 cmp %g5, 3
0x104 be 0x200
0x108 b 0x300
I believe this is what is described on page 55 of the sparc v8 manual as
unpredictable behavior, where a Bicc precedes an unconditional branch.
QEMU actually crashes unless run in GDB. Single stepping will a
