On 15 April 2014 02:33, zhuxiaodong wrote:
> I am a user of qemu. I found that in qemu2.0.0-rc0 the gic model was
> updated. However, it seems loss ability to bind irqs to any specified core
> when the board includes multiple cortex-a9 cores. The problematic codes
> maybe locate at hw/intc
Hi,
I am a user of qemu. I found that in qemu2.0.0-rc0 the gic model was
updated. However, it seems loss ability to bind irqs to any specified core when
the board includes multiple cortex-a9 cores. The problematic codes maybe locate
at hw/intc/arm_gic.c:
50 void gic_update(GICState *s)
