On 13/05/2015 13:21, Edgar E. Iglesias wrote:
>
> It was not clear to me if CPUs should hook into the iommu notification
> system or if we should make the iommu notification code signal changes
> through AS change notifications.
>
> The latter would be easy to get right I guess but we wouldn't
On Wed, May 13, 2015 at 11:28:38AM +0200, Paolo Bonzini wrote:
>
>
> On 13/05/2015 08:41, Edgar E. Iglesias wrote:
> > I think it would be nice if address_space_translate_for_iotlb
> > was allowed to modify the attributes so that an IOMMU in front
> > of a CPU could for example down-grade a secur
On 13/05/2015 08:41, Edgar E. Iglesias wrote:
> I think it would be nice if address_space_translate_for_iotlb
> was allowed to modify the attributes so that an IOMMU in front
> of a CPU could for example down-grade a secure to a non-secure accesse
> (once we add IOMMU support in front of CPUs). I
On Tue, May 12, 2015 at 03:47:00PM +0100, Peter Maydell wrote:
> Resurrecting a six month old thread (and starting with
> a big long quote for context):
>
> On 8 September 2014 at 12:53, Peter Maydell wrote:
> > On 7 September 2014 02:47, Edgar E. Iglesias
> > wrote:
> >> On Thu, Sep 04, 2014 a
Resurrecting a six month old thread (and starting with
a big long quote for context):
On 8 September 2014 at 12:53, Peter Maydell wrote:
> On 7 September 2014 02:47, Edgar E. Iglesias wrote:
>> On Thu, Sep 04, 2014 at 06:47:58PM +0100, Peter Maydell wrote:
>>> tlb_set_page() takes an extra argum
On Mon, Sep 08, 2014 at 12:53:57PM +0100, Peter Maydell wrote:
> On 7 September 2014 02:47, Edgar E. Iglesias wrote:
> > On Thu, Sep 04, 2014 at 06:47:58PM +0100, Peter Maydell wrote:
> >> We introduce the concept of memory transaction attributes,
> >> which are a guest-CPU specific bunch of bits
On 7 September 2014 02:47, Edgar E. Iglesias wrote:
> On Thu, Sep 04, 2014 at 06:47:58PM +0100, Peter Maydell wrote:
>> We introduce the concept of memory transaction attributes,
>> which are a guest-CPU specific bunch of bits (say, a
>> uint32_t). We also allow the CPU to have more than one
>> Ad
On Thu, Sep 04, 2014 at 06:47:58PM +0100, Peter Maydell wrote:
> One of the parts of the ARM TrustZone/Security Extensions
> which the patchsets we've seen so far haven't attempted to
> tackle is the problem of Secure vs NonSecure memory accesses.
> Architecturally, every memory transaction should
On 6 September 2014 01:26, Peter Crosthwaite
wrote:
> On Fri, Sep 5, 2014 at 3:47 AM, Peter Maydell
> wrote:
>> (Another oddball usecase is the Cortex-M split I and D
>> bus for low memory, where instruction and data accesses
>> go out via different buses and might map to different things,
>> bu
On Fri, Sep 5, 2014 at 3:47 AM, Peter Maydell wrote:
> One of the parts of the ARM TrustZone/Security Extensions
> which the patchsets we've seen so far haven't attempted to
> tackle is the problem of Secure vs NonSecure memory accesses.
> Architecturally, every memory transaction should have
> an
One of the parts of the ARM TrustZone/Security Extensions
which the patchsets we've seen so far haven't attempted to
tackle is the problem of Secure vs NonSecure memory accesses.
Architecturally, every memory transaction should have
an S/NS bit accompanying the physical address, effectively
making
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