I am investigating how LW is emulated from target-mips on x86 host.
However, i can not find where the OFFSET is passed in.
case OPC_LW:
save_cpu_state(ctx, 0);
op_ld_lw(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "lw";
break;
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On 6 January 2012 12:45, Xin Tong wrote:
> In qemu soft TLB, there is a MMU modes. what is it and what does it do
> ? I see target-mips, NB_MMU_MODES is defined to be 3, unfortunately,
> there is no comments on what each one of them means in the code.
This distinguishes TLB entries for kernel mod
In qemu soft TLB, there is a MMU modes. what is it and what does it do
? I see target-mips, NB_MMU_MODES is defined to be 3, unfortunately,
there is no comments on what each one of them means in the code.
Thanks
