Fabrice Bellard wrote:
> Thiemo Seufer wrote:
> >Fabrice Bellard wrote:
> >
> >>I just looked at the MIPS file target-mips/op_helper.c and I don't
> >>understand why IRQs need to be handled in op_helper.c:do_mtc0() with reg
> >>= 12.
> >
> >
> >Register 12 is the cp0_status register, it defines w
Thiemo Seufer wrote:
Fabrice Bellard wrote:
I just looked at the MIPS file target-mips/op_helper.c and I don't
understand why IRQs need to be handled in op_helper.c:do_mtc0() with reg
= 12.
Register 12 is the cp0_status register, it defines which interrupts are
masked/enabled/disabled. Btw,
Fabrice Bellard wrote:
> I just looked at the MIPS file target-mips/op_helper.c and I don't
> understand why IRQs need to be handled in op_helper.c:do_mtc0() with reg
> = 12.
Register 12 is the cp0_status register, it defines which interrupts are
masked/enabled/disabled. Btw, I have a patch whic
I just looked at the MIPS file target-mips/op_helper.c and I don't
understand why IRQs need to be handled in op_helper.c:do_mtc0() with reg
= 12. IMHO, the corresponding code should be deleted because the TB is
forced to terminate after mtc0 so that the IRQs can be handled in the
main loop in c
