Thiemo Seufer <[EMAIL PROTECTED]> writes:
> Richard Sandiford wrote:
>> What should the patch do instead for MIPS IV? Enable them unconditionally?
>
> Given that it is currently theoretical, as the only MIPS IV CPU
> supported is the VR5432: Add a comment to the MIPS IV test that it is
> too restr
Richard Sandiford wrote:
> Thiemo Seufer <[EMAIL PROTECTED]> writes:
> > Richard Sandiford wrote:
> >> All MIPS COP1X instructions currently require the FPU to be in 64-bit
> >> mode. My understanding is that this is too restrictive, and that the
> >> base conditions are different for different re
Thiemo Seufer <[EMAIL PROTECTED]> writes:
> Richard Sandiford wrote:
>> All MIPS COP1X instructions currently require the FPU to be in 64-bit
>> mode. My understanding is that this is too restrictive, and that the
>> base conditions are different for different revisions of the ISA:
>>
>> MIPS I
Richard Sandiford wrote:
> All MIPS COP1X instructions currently require the FPU to be in 64-bit
> mode. My understanding is that this is too restrictive, and that the
> base conditions are different for different revisions of the ISA:
>
> MIPS IV:
> COP1X instructions are available when th
All MIPS COP1X instructions currently require the FPU to be in 64-bit
mode. My understanding is that this is too restrictive, and that the
base conditions are different for different revisions of the ISA:
MIPS IV:
COP1X instructions are available when the XX (CU3) bit of the
status regi
