Re: [Qemu-devel] Cortex-M4F Floating Point system registers

2013-03-20 Thread Fabien Chouteau
On 03/20/2013 05:43 PM, Peter Maydell wrote: > On 20 March 2013 16:05, Fabien Chouteau wrote: >> I'm looking at the ARMv7-M profile and the implementation in QEMU. >> Looks like M3 is supported and I'd like to work on M4F (FP context save >> and lazy FP context save). > > This is going to be inter

Re: [Qemu-devel] Cortex-M4F Floating Point system registers

2013-03-20 Thread Peter Maydell
On 20 March 2013 16:05, Fabien Chouteau wrote: > I'm looking at the ARMv7-M profile and the implementation in QEMU. > Looks like M3 is supported and I'd like to work on M4F (FP context save > and lazy FP context save). This is going to be interesting because we don't currently have any mechanisms

[Qemu-devel] Cortex-M4F Floating Point system registers

2013-03-20 Thread Fabien Chouteau
Hello QEMU ARM folks, I'm looking at the ARMv7-M profile and the implementation in QEMU. Looks like M3 is supported and I'd like to work on M4F (FP context save and lazy FP context save). I wonder how the FPU system registers, and more generally how the co-processor registers are implemented in Q