On Thu, 15 Aug 2019 18:24:53 +0200
Paolo Bonzini wrote:
> On 15/08/19 18:07, Igor Mammedov wrote:
> > Looking at Q35 code and Seabios SMM relocation as example, if I see it
> > right QEMU has:
> > - SMRAM is aliased from DRAM at 0xa
> > - and TSEG steals from the top of low RAM when c
On 15/08/19 18:07, Igor Mammedov wrote:
> Looking at Q35 code and Seabios SMM relocation as example, if I see it
> right QEMU has:
> - SMRAM is aliased from DRAM at 0xa
> - and TSEG steals from the top of low RAM when configured
>
> Now problem is that default SMBASE at 0x3 isn't b
On Wed, 14 Aug 2019 16:04:50 +0200
Paolo Bonzini wrote:
> On 14/08/19 15:20, Yao, Jiewen wrote:
> >> - Does this part require a new branch somewhere in the OVMF SEC code?
> >> How do we determine whether the CPU executing SEC is BSP or
> >> hot-plugged AP?
> > [Jiewen] I think this is block
On 15/08/19 11:55, Yao, Jiewen wrote:
> Hi Paolo
> I am not sure what do you mean - "You do not need a reset vector ...".
> If so, where is the first instruction of the new CPU in the virtualization
> environment?
> Please help me understand that at first. Then we can continue the discussion.
The
Hi Paolo
I am not sure what do you mean - "You do not need a reset vector ...".
If so, where is the first instruction of the new CPU in the virtualization
environment?
Please help me understand that at first. Then we can continue the discussion.
Thank you
Yao Jiewen
> -Original Message-
On 14/08/19 15:20, Yao, Jiewen wrote:
>> - Does this part require a new branch somewhere in the OVMF SEC code?
>> How do we determine whether the CPU executing SEC is BSP or
>> hot-plugged AP?
> [Jiewen] I think this is blocked from hardware perspective, since the first
> instruction.
> There
My comments below.
> -Original Message-
> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Wednesday, August 14, 2019 12:09 AM
> To: edk2-devel-groups-io
> Cc: edk2-rfc-groups-io ; qemu devel list
> ; Igor Mammedov ;
> Paolo Bonzini ; Yao, Jiewen
> ; Chen, Yingwen ;
> Nakajima, Jun ;
On 08/13/19 18:09, Laszlo Ersek wrote:
> On 08/13/19 16:16, Laszlo Ersek wrote:
>> (06) Host CPU: (SMM) Save 38000, Update 38000 -- fill simple SMM
>> rebase code.
>>
>> (07) Host CPU: (SMM) Send message to New CPU to Enable SMI.
>
> Aha, so this is the SMM-only register you mention in step
On 08/13/19 16:16, Laszlo Ersek wrote:
> Yingwen and Jiewen suggested the following process.
>
> Legend:
>
> - "New CPU": CPU being hot-added
> - "Host CPU": existing CPU
> - (Flash):code running from flash
> - (SMM): code running from SMRAM
>
> Steps:
>
> (01) New CPU: (Flash) enter res
Hi,
this message is a problem statement, and an initial recommendation for
solving it, from Jiewen, Paolo, Yingwen, and others. I'm cross-posting
the thread starter to the ,
and lists. Please use "Reply All" when
commenting.
In response to the initial posting, I plan to ask a number of question
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