On 25 May 2016 at 13:33, Karthik wrote:
> Does the qemu implements cache emulation?
> I did see some comments saying otherwise.
No, we don't emulate functional caches. This means that all
the operations for "flush cache" etc can be no-ops. They
do still have to actually exist and not UNDEF, thoug
Understood. Thank you for the clarifications.
Best regards,
Karthik
On Wed, May 25, 2016 at 6:05 PM, Peter Maydell
wrote:
> On 25 May 2016 at 13:33, Karthik wrote:
> > Does the qemu implements cache emulation?
> > I did see some comments saying otherwise.
>
> No, we don't emulate functional ca
Does the qemu implements cache emulation?
I did see some comments saying otherwise.
Best regards,
Karthik
On Wed, May 25, 2016 at 5:57 PM, Peter Maydell
wrote:
> On 25 May 2016 at 06:44, Karthik wrote:
> > Hi,
> >
> > CPU: Cortex R5F
> >
> > I have this instruction that invalidates the entire
On 25 May 2016 at 06:44, Karthik wrote:
> Hi,
>
> CPU: Cortex R5F
>
> I have this instruction that invalidates the entire data cache
>
> MCR p15, 0, r0, c15, c5, 0
>
>
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460c/Chdhgibd.html
>
> This instruction generates undefined exce
Hi,
CPU: Cortex R5F
I have this instruction that invalidates the entire data cache
MCR p15, 0, r0, c15, c5, 0
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460c/Chdhgibd.html
This instruction generates undefined exception, and further debugging
showed it is because the co-pr
