@suse.de]
Sent: Monday, May 26, 2014 11:18 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: James Hogan; Petar Jovanovic; aurel...@aurel32.net; r...@twiddle.net
Subject: Re: [Qemu-devel] [v2 PATCH] target-mips: implement UserLocal Register
Am 26.05.2014 19:28, schrieb Petar Jovanovic:
> From: Petar
On 27/05/14 17:01, James Hogan wrote:
> On 26/05/14 22:18, Andreas Färber wrote:
>> Am 26.05.2014 19:28, schrieb Petar Jovanovic:
>>> RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a
>>> 1 to enable unprivileged access to the register.
>>>
>>> Signed-off-by: Petar Jovanov
On 05/27/2014 10:28 AM, Petar Jovanovic wrote:
>> The normal way to handle this is to end the translation block whenever we
>> issue
>> an instruction that could (unpredictably) affect how the TB is translated.
>
>> In the mips translator, this is done via "ctx->bstate = BS_STOP".
>> There are pl
> The normal way to handle this is to end the translation block whenever we
> issue
> an instruction that could (unpredictably) affect how the TB is translated.
> In the mips translator, this is done via "ctx->bstate = BS_STOP".
> There are plenty of examples within gen_mtc0 already.
Yes, I am a
On 05/27/2014 09:46 AM, Petar Jovanovic wrote:
> Can you please add more thoughts on this? Within the same translation block,
> we can have an instruction that alters HWrena (mtc0) and rdwhr instruction
> that
> will behave differently based on content of HWrena.
The normal way to handle this is
> That's what tb->flags and env->hflags. An encoding of cpu state at translation
time.
Can you please add more thoughts on this? Within the same translation block,
we can have an instruction that alters HWrena (mtc0) and rdwhr instruction that
will behave differently based on content of HWrena.
P
On 05/27/2014 02:47 AM, James Hogan wrote:
> I agree for the Config3 bit that it shouldn't change during execution of
> the guest so can be done at translation time, but I'm not convinced it's
> worth wasting tb->flags bits for CP0_HWREna state which the guest OS is
> free to change at any time, ju
On 26/05/14 22:18, Andreas Färber wrote:
> Am 26.05.2014 19:28, schrieb Petar Jovanovic:
>> RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a
>> 1 to enable unprivileged access to the register.
>>
>> Signed-off-by: Petar Jovanovic
>> ---
>> v2:
>> - Defined MIPS_HFLAG_CP0
Hi Richard,
On 27/05/14 03:38, Richard Henderson wrote:
> On 05/26/2014 07:32 PM, Petar Jovanovic wrote:
>>
>>
>> From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson
>> [r...@twiddle.net]
>> Sent: Tuesday, May 27, 2014 3:35 AM
>> To:
On 05/26/2014 07:32 PM, Petar Jovanovic wrote:
>
>
> From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson
> [r...@twiddle.net]
> Sent: Tuesday, May 27, 2014 3:35 AM
> To: Petar Jovanovic; Petar Jovanovic; qemu-devel@nongnu.org
> Cc: a
From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson
[r...@twiddle.net]
Sent: Tuesday, May 27, 2014 3:35 AM
To: Petar Jovanovic; Petar Jovanovic; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; James Hogan
Subject: Re: [v2 PATCH] targ
On 05/26/2014 06:21 PM, Petar Jovanovic wrote:
> Because we do not know the content of CP0_HWREna.
We can know the same way we know the content of CP0_Config3.
r~
From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson
[r...@twiddle.net]
Sent: Tuesday, May 27, 2014 12:53 AM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net; James Hogan
Subject: Re: [v2 PATCH] tar
On 05/26/2014 10:28 AM, Petar Jovanovic wrote:
> void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
> {
> -env->CP0_HWREna = arg1 & 0x000F;
> +uint32_t mask = 0x000F;
> +
> +if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
> +mask |= 0x2000;
> +}
> +
> +
Am 26.05.2014 19:28, schrieb Petar Jovanovic:
> From: Petar Jovanovic
>
> From MIPS documentation (Volume III):
>
> UserLocal Register (CP0 Register 4, Select 2)
> Compliance Level: Recommended.
>
> The UserLocal register is a read-write register that is not interpreted by
> the hardware and co
From: Petar Jovanovic
>From MIPS documentation (Volume III):
UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.
This register
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