Hi all,
I think, from coreboot code, the MMIO reservation is done through an
MCFG table. I can't see one in Qemu but I don't have a clue how to
extend it. There's literally nothing about MCFG online neither do I
have an org that's a member of pcisig.
Could someone have the docs describing MCFG ?
Hi all,
I recall I saw IVRS filling code in the coreboot for one of the boards
supported. David, you may want to have a look there.
Valentine
(from the phone)
On Jan 14, 2016 9:29 PM, "Kevin O'Connor" wrote:
> On Thu, Jan 14, 2016 at 12:09:46PM +0200, Michael S. Tsirkin wrote:
> > On Thu, Jan 1
On Thu, Jan 14, 2016 at 07:29:40PM +0300, David kiarie wrote:
> On Thu, Jan 14, 2016 at 7:19 PM, Jan Kiszka wrote:
> > On 2016-01-14 17:09, David kiarie wrote:
> >> On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka wrote:
> >>> On 2016-01-14 16:39, Michael S. Tsirkin wrote:
> On Thu, Jan 14, 2016
On Thu, Jan 14, 2016 at 12:09:46PM +0200, Michael S. Tsirkin wrote:
> On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote:
> > Add IVRS table for AMD IO MMU. Also reverve MMIO
>
> reserve?
>
> > region for IO MMU via ACPI
>
>
> It does not look like you reserve anything.
>
> Pls add a
On Thu, Jan 14, 2016 at 7:19 PM, Jan Kiszka wrote:
> On 2016-01-14 17:09, David kiarie wrote:
>> On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka wrote:
>>> On 2016-01-14 16:39, Michael S. Tsirkin wrote:
On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote:
> On Thu, Jan 14, 2016 at 1
On 2016-01-14 17:09, David kiarie wrote:
> On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka wrote:
>> On 2016-01-14 16:39, Michael S. Tsirkin wrote:
>>> On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote:
On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin
wrote:
> On Thu, Jan
On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka wrote:
> On 2016-01-14 16:39, Michael S. Tsirkin wrote:
>> On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote:
>>> On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin wrote:
On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote:
>>
On 2016-01-14 16:39, Michael S. Tsirkin wrote:
> On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote:
>> On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin wrote:
>>> On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote:
Add IVRS table for AMD IO MMU. Also reverve MMIO
>>>
>
On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote:
> On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin wrote:
> > On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote:
> >> Add IVRS table for AMD IO MMU. Also reverve MMIO
> >
> > reserve?
>
> Yeah, typo.
>
> >
> >> region fo
On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin wrote:
> On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote:
>> Add IVRS table for AMD IO MMU. Also reverve MMIO
>
> reserve?
>
>> region for IO MMU via ACPI
>
>
> It does not look like you reserve anything.
>
> Pls add a link to hardwa
On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin wrote:
> On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote:
>> Add IVRS table for AMD IO MMU. Also reverve MMIO
>
> reserve?
Yeah, typo.
>
>> region for IO MMU via ACPI
>
>
> It does not look like you reserve anything.
>
> Pls add a
On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote:
> Add IVRS table for AMD IO MMU. Also reverve MMIO
reserve?
> region for IO MMU via ACPI
It does not look like you reserve anything.
Pls add a link to hardware spec (in
the device implementation) so we can check
what does real hardw
On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote:
> Add IVRS table for AMD IO MMU. Also reverve MMIO
> region for IO MMU via ACPI
>
> Signed-off-by: David Kiarie
> ---
> hw/i386/acpi-build.c| 96
> +
> include/hw/acpi/acpi-defs.h |
Add IVRS table for AMD IO MMU. Also reverve MMIO
region for IO MMU via ACPI
Signed-off-by: David Kiarie
---
hw/i386/acpi-build.c| 96 +
include/hw/acpi/acpi-defs.h | 55 ++
2 files changed, 151 insertions(+)
diff --git
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