Re: [Qemu-devel] [RFC v1 11/13] target-ppc: add maddld instruction

2016-07-21 Thread Richard Henderson
On 07/21/2016 12:24 PM, Richard Henderson wrote: On 07/18/2016 10:35 PM, Nikunj A Dadhania wrote: +static void gen_maddld(DisasContext *ctx) +{ +TCGv_i64 lo = tcg_temp_new_i64(); +TCGv_i64 hi = tcg_temp_new_i64(); +TCGv_i64 t1 = tcg_temp_new_i64(); +TCGv_i64 t2 = tcg_temp_new_i64

Re: [Qemu-devel] [RFC v1 11/13] target-ppc: add maddld instruction

2016-07-20 Thread Richard Henderson
On 07/18/2016 10:35 PM, Nikunj A Dadhania wrote: +static void gen_maddld(DisasContext *ctx) +{ +TCGv_i64 lo = tcg_temp_new_i64(); +TCGv_i64 hi = tcg_temp_new_i64(); +TCGv_i64 t1 = tcg_temp_new_i64(); +TCGv_i64 t2 = tcg_temp_new_i64(); +TCGv_i64 zero = tcg_const_i64(0); +TC

[Qemu-devel] [RFC v1 11/13] target-ppc: add maddld instruction

2016-07-18 Thread Nikunj A Dadhania
maddld: Multiply-Add Low Doubleword Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the lower dword in the target register(RT). Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 30 ++ 1 file changed,