> From: Peter Xu [mailto:zh...@redhat.com]
> Sent: Tuesday, July 9, 2019 12:48 PM
> To: Liu, Yi L
> Cc: qemu-devel@nongnu.org; m...@redhat.com; pbonz...@redhat.com;
> alex.william...@redhat.com; eric.au...@redhat.com;
> da...@gibson.dropbear.id.au; tianyu@intel.com; Tian, Kevin
> ; Tian, Jun J
On Fri, Jul 05, 2019 at 07:01:42PM +0800, Liu Yi L wrote:
> +static bool vtd_process_pasid_desc(IntelIOMMUState *s,
> + VTDInvDesc *inv_desc)
> +{
> +if ((inv_desc->val[0] & VTD_INV_DESC_PASIDC_RSVD_VAL0) ||
> +(inv_desc->val[1] & VTD_INV_DESC_PASIDC_RS
This patch adds PASID cache flush emulation framework. Per Intel VT-d 3.0
spec, PASID cache invalidation under caching-mode provides a mechanism
software Intel VT-d(vIOMMU) implementations to track guest PASID bind/unbind
operations. This is a key part of vIOMMU support for guest SVA. And this
patc
