Re: [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction

2016-07-23 Thread Richard Henderson
On 07/23/2016 11:38 AM, Nikunj A Dadhania wrote: > (2) You need to use ULL for 32-bit hosts, or casts, e.g. Having it defined only for 64-bit 32-bit *host*, not 32-bit guest. I.e. i686 host emulating ppc64 guest. r~

Re: [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction

2016-07-22 Thread Nikunj A Dadhania
Richard Henderson writes: > On 07/23/2016 12:58 AM, Nikunj A Dadhania wrote: >> Richard Henderson writes: >> >>> On 07/18/2016 10:35 PM, Nikunj A Dadhania wrote: +tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF); +for (i = 0; i < 64; i += 8) { +tcg_gen_shri_tl

Re: [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction

2016-07-22 Thread Richard Henderson
On 07/23/2016 12:58 AM, Nikunj A Dadhania wrote: Richard Henderson writes: On 07/18/2016 10:35 PM, Nikunj A Dadhania wrote: +tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF); +for (i = 0; i < 64; i += 8) { +tcg_gen_shri_tl(t0, arg1, i); +tcg_gen_andi_tl(t0, t0, 0x

Re: [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction

2016-07-22 Thread Nikunj A Dadhania
Richard Henderson writes: > On 07/18/2016 10:35 PM, Nikunj A Dadhania wrote: >> +tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF); >> +for (i = 0; i < 64; i += 8) { >> +tcg_gen_shri_tl(t0, arg1, i); >> +tcg_gen_andi_tl(t0, t0, 0xFF); >> +tcg_gen_brcond_tl(TCG_

Re: [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction

2016-07-21 Thread David Gibson
On Mon, Jul 18, 2016 at 10:35:13PM +0530, Nikunj A Dadhania wrote: > From: Swapnil Bokade > > Search a byte in the stream of 8bytes provided in the register > > Signed-off-by: Sandipan Das > [ Modified the logic to use lesser temporaries ] > Signed-off-by: Nikunj A Dadhania rth's reference ma

Re: [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction

2016-07-21 Thread Nikunj A Dadhania
Richard Henderson writes: > On 07/18/2016 10:35 PM, Nikunj A Dadhania wrote: >> +tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF); >> +for (i = 0; i < 64; i += 8) { >> +tcg_gen_shri_tl(t0, arg1, i); >> +tcg_gen_andi_tl(t0, t0, 0xFF); >> +tcg_gen_brcond_tl(TCG_

Re: [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction

2016-07-20 Thread Richard Henderson
On 07/18/2016 10:35 PM, Nikunj A Dadhania wrote: +tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF); +for (i = 0; i < 64; i += 8) { +tcg_gen_shri_tl(t0, arg1, i); +tcg_gen_andi_tl(t0, t0, 0xFF); +tcg_gen_brcond_tl(TCG_COND_EQ, src1, t0, l1); +} +tcg_gen

Re: [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction

2016-07-18 Thread Nikunj A Dadhania
Nikunj A Dadhania writes: > From: Swapnil Bokade > > Search a byte in the stream of 8bytes provided in the register > > Signed-off-by: Sandipan Das Should have been: Signed-off-by: Swapnil Bokade > [ Modified the logic to use lesser temporaries ] > Signed-off-by: Nikunj A Dadhania Regards

[Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction

2016-07-18 Thread Nikunj A Dadhania
From: Swapnil Bokade Search a byte in the stream of 8bytes provided in the register Signed-off-by: Sandipan Das [ Modified the logic to use lesser temporaries ] Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 27 +++ 1 file changed, 27 insertions(+) diff